The A/D converters are interfaces between analog signal domain and digital signal domain. Conventionally, the precise A/D converters need accurate analog process to achieve high resolution. Hence, the A/D converters with high precision can not easily implemented and realized in VLSI systems.
Recently, due to the development of oversampling and feedback control techniques applied on A/D conversion, the analog circuits of sigma-delta A/D converters which adopt simple and high tolerance components can avoid the drawbacks of conventional A/D converters. This new converter called sigma-delta A/D converter is composed of modulators and digital filters. When the order of the modulator is increased, the resolution of the whole system is increased and the nonlinear effects which always occur in the low order modulator such as limit cycle and pattern noise can be avoided in contrast, the high order modulators generally suffer from the unstable problem and the control coefficients of the modulators being too large or small, which causes the difficulty of implementing VLSI circuits. Hence, how to design a modulator of sigma-delta A/D converter, especially in high order architecture, is the most important challenge. K. C. Chao et al. in their article entitled "A High Order Topology for Interpolative Modulators for Oversampling A/D converters", IEEE Trans. on Circuits and Systems, vol. 37, Mar. 1990, disclose a topology called "Follow the Leader" for sigma-delta modulators, which is a very popular design methodology. However, this topology suffers from the complexity of system architecture and extreme of control coefficients when the topology is synthesized. This is the reason why this architecture is very difficult and costly for VLSI circuits realization. S. M. Moussavi et al. in their article entitled "High-Order Single-Stage Single-Bit Oversampling A/D Converter Stabilized with Local Feedback Loops", IEEE Trans. on Circuits and Systems II, vol. 41, Jan. 1994, disclose a different methodology design of system architecture in order to solve the stability problem which occurs when a sigma-delta modulator is implemented in a high-order form. However, the same problems such as complicated architecture, high cost, and difficult VLSI circuits realization occur.
U.S. Pat. No. 5,298,900 entitled "Sigma-Delta Modulator", invented by Manfred Mauthe and Rudolf Koch, discloses a cascaded sigma-delta modulator topology which is characterized by the combination of a second-order modulator and a first-order modulator to improve the problems of stability, noise and requirement of extra precise circuits in a third-order modulator. However, this topology has a disadvantage which is the requirement of matching components.
U.S. Pat. No. 5,061,928 entitled "System and Method of Scaling Error Signals of Caseload Second Order Modulators", invented by Teppo J. Karema, Tapani J. Ritoniemi and Aaine H. Tenhunen, discloses another cascaded sigma-delta modulator architecture which is characterized by the combination of adjoining two second-order modulators to avoid the realization of adjoining many high precision first order modulators and a requirement of special circuits in the first-order modulators. However, the disadvantage of the modulator disclosed in the aforesaid U.S. Pat. No. 5,298,900 still exists in this type modulator.
Therefore, a high-order (fourth-order) sigma-delta modulator with high resolution, absolute stable, insensitive to the matching of circuit components, low cost and easy implementation of VLSI circuits is still an urgent need in the art.